Predicted iteration in decimal division

ABSTRACT

Decimal divide apparatus capable of performing divide iterations in accordance with either the restoring technique (wherein the sign of each partial dividend is made to conform to the sign of the previous partial dividend) or the nonrestoring technique (wherein each successive partial dividend is utilized unaltered). For each iteration, the technique that is likely to be more efficient is selected. The selection is based upon the high-order digits of the divisor and the partial dividend and the sign of the partial dividend.

United States Patent Robert A. Nelson inventor [56] References Cited A l gggi s UNITED STATES PATENTS Filed Jan 13,1967 2.6l5,624 10/1952 Brand etal. 235/162 Patented July 6, 1971 OTHER REFERENCES Assignee International Business Machines Pages 273 275 and 277, 1961 Richards, ARITHMETIC Corporation OPERATIONS, call letters (7888.3 R5CT8.

Armonlr N.Y.

Primary Exammer-Eugene G. Botz Continuation-impart of application Ser. No. I

p now abandoned At omeys amfin and Jancm and Gunter A. Hauptman ABSTRACT: Decimal divide apparatus capable of performing divide iterations in accordance with either the restoring technique (wherein the sign of each partial dividend is made ;Egi ;:g p IN DECIMAL DIVISION to conform to the sign of the previous partial dividend) or the "wing nonrestoring technique (wherein each successive partial U.S.Cl 235/160 dividend is utilized unaltered). For each iteration, the lnt.Cl I I G06f 7/44 technique that is likely to be more efficient is selected. The Field of Search 235/164, selection is based upon the high-order digits of the divisor and 175, 160 the partial dividend and the sign of the partial dividend.

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PATENTED JUL 6 I971 SHEET 01 0F 50 FIG.1

PATENTEU JUL 6m: 3; 591. 786

saw on 0F 50 PATENIEI] JUL 6 I971 FIG. 12

FIG. 59

SHEET 08 DF- 50 THIS FIGURE IS ILLUSTRATIVE OF A LIKE-NUMBERED FIGURE WHICH IS SHOWN IN DETAIL IN SAID ENVIRONMENTAL SYSTEM,

LARGE SCALE DATA PROCESSING SYSTEM,

SERIAL NO. 609238 FILED 0N JANUARY I3, I967 PATENTEDJIIL BIHII 3591.786 sum 10m 50 I I I TH THIS FIGURE IS ILLUSTRATIVE OF A LIKE-NUMBERED FIGURE WHICH IS SHOWN IN DETAIL IN SAID ENVIRONMENTAL SYSTEM, LARGE SCALE DATA PROCESSING SYSTEM,

SERIAL NO. 609236 FILED 0N JANUARY I5, I967 THIS FIGURE IS ILLUSTRATIVE OF A LIKE-NUMBERED FIGURE WHICH IS SHOWN IN DETAIL IN SAID ENVIRONMENTAL SYSTEM,

LARGE SCALE DATA PROCESSING SYSTEM,

SERIAL NO. 609 238 FILED ON JANUARY I3. I967 PATENIED .101 6 1011 SHEET 11 [1F 50 F|(; 68 1 UNIT SCAN W01 W02 1 W05 W04 W05 W06 0 0 o 0 0 2''. S IL. Ii: 11L". I II}: 1 5.1L. .IL'. r 25 25 T 101 GPR GPR p1 CHASP P50 0105 11101 1 010 CYC6 WAIT 5111 Psw 1111110v1110 11011 01111 51 1 51 51 CONS 111111 1111 111 10011 0-1 0-1 "0-1 1x1 101 0-15 8 0-15 E 0-15 IPGM 1111 1 T P 16-25 P 16-25 F 16-25 11110- IRPT 0-1 H 0-1 110 2* 0-15 REG 11-15 59 1 16-25 P 16-25 1 59 i 50 4o 1 o 1 0 1 o 0116111161 I 011011100 LC BFE TSTS 0111 11 AFM $00011 0111 BOP 0P SSOP L BR 11 11:11o10v +11 110W 1 +111 REG 20 001 P 0-1 1010 REG 21 1 x10 01 0s REG 22 W x10 510 01111111 ICR SAR H REG A U) CORR p 1 0 10 v11 11011 1 A 111v 11 0 11V 12 111 8161 011001 N 11 1x1 SIG 2 0111 1111 W 5 1 01111211 1 2 OPF 5 IE 5 11001 101 LD 1 61 010 11110011 111 1 1 00511 1111 1611 111 2 LE 0001 65 1 25 11 1x1s166 1111-1112 01111011 PATENTED JUL 6 I97! SHEET 12 HF 50 w: o I; 52:; s; as g 2 35 at All E3 of; ifigs Em 3 mm L l m m "E 4 2 2 :E 7: :5; :3 mm m $55 0: .5 f; wmwmwzt SE28 k wifi m E 1 NM 2 E ifigwwf malt; $1: 3; 8 88 #3 03m no LBJ: 3; i; 5% m2. E To mill: 3; 2 3 m s z o 2 E8 240m .:2: m

PATENTEDJUL 6I97I 3,591,786

SHEET 13 DF 50 FIG. 70

THIS FIGURE IS ILLUSTRATIVE OF A LIKE-NUMBERED FIGURE WHICH IS SHOWN IN DETAIL IN SAID ENVIRONMENTAL SYSTEM,

LARGE SCALE DATA PROCESSING SYSTEM,

SERIAL NO. 609238 FILED 0N JANUARY I3, I967 FIG. 71

THIS FIGURE IS ILLUSTRATIVE OF A LIKE-NUMBERED FIGURE WHICH IS SHOWN IN DETAIL IN SAID ENVIRONMENTAL SYSTEM,

LARGE SCALE DATA PROCESSING SYSTEM,

SERIAL NO.6OQ2Z & FILED 0N JANUARY I3, I967 PATENIED JUL 6 (97:

Sum 1701' so GR 81 ADR FIG. 75

K REG 0-51 DEC H DEC 1 DEC 1R2 SEL GR (16 LINES) IB SEL GR (16 LINES) BRI SEL GR 116 LINES) BRI +1 SEL GR (8 LINES) ERI SEL GR IN (16 LINES) GENERAL REGISTERS (GR) ADDRESS ADDER (AA) LCH INGR

25 I UNIT GIRLS GS REG E UNIT GIRLS z 24 PSW 54-59 24-51 T0 IOP RIRZ-X 24-27TOKEYS I 'I (Is- UNIT ADR T0 CH (UABOL I UNIT 125456 SELGH PATENIED JUL 6 ISII SHEET 180E 5O FIG. 76

I I THRU I THIS FIGURE IS ILLUSTRATIVE OF A LIKE-NUMBERED FIGURE WHICH Is wow I IN DETAIL IN SAID ENVIRONMENTAL SYSTEM, I LARGE scALE DATA PROCESSING SYSTEM, I SERIAL N0. @0923s I FILED 0N JANUARY I3,I%7 I I I 'I I I l I I I FIG. 372 I I PATENTEU JUL 6 I97! SHEET (EXT K REG L REG v F L R2 Z INCR 0 FROM DA 555% 599 H B 00/08 a FL Y 5 D6 BELOW H V 400 L86 R80 REG Y 8 our KEY E: 598 MR LOH IN GATE T PTRG: 375 374 3 PTR IOP (845) 5 (1 UNIT) 1 77-.EDIT R 5 DEC 00 (EXT C: REG SIGN UNIT) 59] DET 51s 80(2-6) 5 3 a 1 840R" (E UNIT) GEN R R n 378 VFL T0 AA A05 PAR ADJ L00 RDG 8 PSW GATE 401 585 585,584 581 580 CROSS 444425-54) 1 5 m0 (I UNIT) p30 (0-7) 1 R. i

H REG(2 (I W T/C +6 ma l 385 DECIMAL T S DDER H REO (19-20) LCH LOH I Q 86 Q%DAE)R I UNIT) 404 404 DEC com I 588 58? I PAR CARRY I GEN |RcR INCR W 588 T 5 WE REG RE0 H 408 408 H 19,20,P T PTR o EA GT LBG E UNIT (ABOVE) K BUS GATE 3 U TO IN K BUS (T0 R REG E umn 

1. A divide apparatus, comprising: arithmetic means for performing division; means to compare a divisor and a dividend; and means responsive to said last named means to cause said arithmetic means to perform a restoring type divide iteration or a nonrestoring type divide iteration, alternatively.
 2. The device described in claim 1, additionally comprising: shift means for shifting the divisor with respect to the dividend; and iteration control means for successively causing said restoring or nonrestoring divide iteration, alternatively, interspersed with operation of said shift means.
 3. In a data processing system, a divide apparatus, comprising: a pair of registers for holding a dividend and a divisor; comparing means responsive to said registers for comparing the dividend and the divisor; arithmetic means responsive to said registers for performing arithmetic operations on the contents thereof, said arithmetic means capable, in response to particular control, to restore a true or complement dividend to its previous complement or true form or to retain said dividend in its true or complement form, alternatively; and means responsive to said comparing means for supplying said particular control to said arithmetic means.
 4. A decimal divider, comprising: arithmetic means for performing restoring type divide iterations and for performing nonrestoring type divide iterations; and means for selecting between the restoring and nonrestoring iterations of said arithmetic means.
 5. The device described in claim 4, additionally comprising: shift means for shifting the divisor with respect to the dividend; and iteration control means for successively causing said restoring or nonrestoring divide iterations, alternatively, interspersed with operation of said shift means.
 6. A divide apparatus, comprising: arithmetic means for performing division; means to compare the first digit of a divisor and the first digit of a dividend; and means responsive to said last named means to cause said arithmetic means to perform a restoring type divide iteration or a nonrestoring type divide iteration, alternatively.
 7. The device described in claim 6, additionally comprising: shift means for shifting the divisor with respect to the dividend; and iteration control means for successively causing said restoring or nonrestoring divide iterations, alternatively, interspersed with operation of said shift means.
 8. In a data processing system, a divide apparatus, comprising: a pair of registers for holding a dividend and a divisor; comparing means responsive to said registers for comparing the first digit of a dividend and the first digit of a divisor; arithmetic means responsive to said registers for performing arithmetic operations on the contents thereof, said arithmetic means capable, in response to particular control, to perform restoring type divide iterations or nonrestoring type divide iterations, alternatively; and means responsive to said comparing means for supplying said particular control to said arithmetic means.
 9. The device described in claim 8, additionally comprising: shift means for shifting the divisor with respect to the dividend; and iteration control means for successively causing said restoring or nonrestoring divide iterations, alternatively, interspersed with operation of said shift means.
 10. A decimal divider, comprising: arithmetic means for performing restoring type divide iterations and nonrestoring-type divide iterations; means for comparing the first digits of the divisor and dividend; and means responsive to said last named means for selecting between the restoring and nonrestoring iterations of said arithmetic means.
 11. The device described in claim 10, additionally comprising: shift means for shifting the divisor with respect to the dividend; and iteration control means for successively causing said restoring or nonrestoring divide iterations, alternatively, interspersed with operation of said shift means.
 12. A divide apparatus comprising: register means for holding a divisor and a dividend; comparing means for comparing said divisor and dividend; arithmetic means operatively connected to said register means for performing arithmetic operations on the contents thereof, said arithmetic means capable of performing restoring type divide iterations or nonrestoring-type divide iterations, alternatively; indicating means for manifesting a signal indicative of the true or complement form of a dividend; and control means having an output operatively connected to said arithmetic means and inputs operatively connected to said comparing means and said indicating means; said control means being responsive to at least a first predetermined combination of signals from said comparing means and said indicating means to cause said arithmetic means to perform a restoring type of divide iteration; said control means also being responsive to at least a second predetermined combination of signals from said comparing means and said indicating means to cause said arithmetic means to perform a nonrestorIng type of divide iteration. 